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CHD408LVS-55,70 CHD408LVW-55,70
Rev 2.2 Jul'03
4M -BIT (512K-WORD BY 8-BIT) SuperT-SRAMTM LOW-POWER ASYNCHRONOUS SRAM
DESCRIPTION
The CHD408L is a family of low voltage, low power 4Mbit static RAMs organized as 512K-words by 8-bit, designed with Cascade's patent pending SuperT-SRAMTM technology, fabricated with low-power 0.18m process technology. The CHD408LVS is designed specifically for low-power applications such as mobile cellular phones, personal digital assistants and other battery-operated products. CHD408LVS -55,70 is packaged in sTSOP-I packages, with normal and reverse lead-bending. sTSOP-I packages are available in dimensions of 8x12mm and 8x20mm.
FEATURES
* Low power Low active and standby power for hand-held applications.
Single power supply. 55ns or 70ns access time 100% compatible with JEDEC asynchronous SRAM. No clocks, no refresh. No timing restrictions. No special power-up sequence requirement. Direct TTL compatibility for all inputs and outputs.
* High Performance * Compatibility
* Technology
Designed with Cascade's patent pending SuperT-SRAMTM technology. - Fabricated with low-power 0.18m process technology. * Extended temperature range -40 ~ 85C .
PART NAME TABLE & KEY SPEC SUMMARY
Max. Access Time @ 2.7V 70ns 55ns Standby Icc Max @ 3.0V 85C 35 A 35 A Active Icc 3.0V 10MHz 8mA 8mA
Power Supply
Part Name
2.7V ~ 3.6V 3.0V ~ 3.6V
CHD408LVx-70 CHD408LVx-55
PART SELECTION TABLE
w
w
Part Name
Package
Lead Bending
w
.D
CHD408LVS-55,70
8x12mm STSOP-I 8x12m m STSOP-I 8x20mm STSOP-I 8x20mm STSOP-I
Normal Reverse Normal Reverse
at aS
CHD408LVS-55,70-R CHD408LVW-55,70
CHD408LVW-55,70-R
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Deutron Electronics Corporation
8F, 68, SEC. 3, NAKING E. RD., TAIPEI 104, TAIWAN, R.O.C.
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CHD408LVS-55,70 CHD408LVW-55,70
Rev 2.2 Jul'03
4M -BIT (512K-WORD BY 8-BIT) SuperT-SRAMTM LOW-POWER ASYNCHRONOUS SRAM
PIN CONFIGURATION
(TOP VIEW)
A11 A9 A8 A13 W A17 A15 VCC A18 A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
(TOP VIEW)
OE A10 S DQ8 DQ7 DQ6 DQ5 DQ4 GND DQ3 DQ2 DQ1 A0 A1 A2 A3 A4 A5 A6 A7 A12 A14 A16 A18 VCC A15 A17 W A13 A8 A9 A11
16 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
CHD408LV
CHD408LV-R
A3 A2 A1 A0 DQ1 DQ2 DQ3 GND DQ4 DQ5 DQ6 DQ7 DQ8 S A10 OE
32 Pin sTSOP(I)
Reverse 32 Pin sTSOP(I)
Pin A0~A18 DQ1 ~ DQ8
Function Address input Data input / output Chip select input Write control input Output enable input Pow er supply Ground supply
S
W
OE VCC
GND
Deutron Electronics Corporation
8F, 68, SEC. 3, NAKING E. RD., TAIPEI 104, TAIWAN, R.O.C.
2
CHD408LVS-55,70 CHD408LVW-55,70
Rev 2.2 Jul'03
4M -BIT (512K-WORD BY 8-BIT) SuperT-SRAMTM LOW-POWER ASYNCHRONOUS SRAM
FUNCTIONAL DESCRIPTION
CHD408LVS -55/70 (-R) is organized as 512K-words by 8-bit. These devices operate on a single power supply, and are directly TTL compatible to both input and output. The design uses fully asynchronous static circuits, requiring no clocks, no refresh, and no special power-up sequence. The operation modes are determined by a combination of the device control inputs S , W and OE . Each mode is summarized in the function table. A write operation is executed whenever the low level W overlaps with the low level S . The address (A0~A18) must be set up before the write cycle and must be stable during entire cycle. A read operation is executed by setting W at a high level and OE at a low level while S is in an active state. When setting S at a high level, the chip is in a non-select mode. In this mode, the output stage is in a high-impedance state, allowing OR -tie with other chips. When OE is at a high level, the output stage is in a high-impedance state.
FUNCTION TABLE
S
OE
W
DQ1-8 Z
(2)
Mode Deselected Output disabled read write
Power Standby Active Active Active
H L L L
X
(1)
X H H L
H L X
Z Data out Data in
Notes :
(1) X means don't-care, but must drive to either high or low.
(2) Z means high impedance state.
Deutron Electronics Corporation
8F, 68, SEC. 3, NAKING E. RD., TAIPEI 104, TAIWAN, R.O.C.
3
CHD408LVS-55,70 CHD408LVW-55,70
Rev 2.2 Jul'03
4M -BIT (512K-WORD BY 8-BIT) SuperT-SRAMTM LOW-POWER ASYNCHRONOUS SRAM
ABSOLUTE MAXIMUM RATINGS
Parameter VCC VI VO PD Tsolder Tstor Toper Power Supply Voltage Input Voltage Output Voltage Power Dissipation Soldering Temperature Storage Temperature Operating Temperature Value -0.4 to 4.6 -0.4* to VCC+0.5 (max 4.6) 0 to VCC 0.5 260 -65 to 150 -40 to 85 Unit V V V W C C C * -3V for AC pulse (<30ns) Notes
DC ELECTRICAL CHARACTERISTIC S (T = -40 to 85C)
Parameter VCC VIH VIL VOH VOL II IO Power Supply Voltage Input High Voltage Input Low Voltage High-Level Output Voltage Low-level Output Voltage Input Leakage Current Output Leakage Current IOH=-1mA IOL=2mA VI=0~VCC Output disabled. VI/O=0~VCC Conditions Min 2.7/3.0 2.2 -0.4* VCC-0.4 Typ Max 3.6 Vcc+0.4 0.6 0.4 1 1 Units V V V V V A A
* -3V for AC pulse (<= 30ns)
POWER CONSUMPTION CHARACTERISTICS
Parameter ICC1 10MHz CMOS-Level Active Current at f=10MHz CMOS-Level Active Current at f=1MHz TTL-Level Active Current at f=10MHz TTL-Level Active Current at f=1MHz Standby Current ( CMOS Level ) Standby Current ( TTL Level ) Conditions Output open. All inputs = 0.2V or VCC-0.2V Output open. All inputs = 0.2V or VCC-0.2V Output open. All inputs = VIL or VIH Output open. All inputs = VIL or VIH Typ Max (3.0V) 8 Max (3.6V) 10 Units mA
-
ICC1 1MHz ICC2 10MHz ICC2 1MHz ISB1
-
2 9 3 35
3 11 4 60
mA mA mA A
S = VCC-0.2V All other inputs = 0.2 or VCC-0.2V
S = VIH All other inputs = VIH or VIL
ISB2
-
0.3
-
mA
Deutron Electronics Corporation
8F, 68, SEC. 3, NAKING E. RD., TAIPEI 104, TAIWAN, R.O.C.
4
CHD408LVS-55,70 CHD408LVW-55,70
Rev 2.2 Jul'03
4M -BIT (512K-WORD BY 8-BIT) SuperT-SRAMTM LOW-POWER ASYNCHRONOUS SRAM
CAPACITANCE
Parameter CI CO Input Capacitance Output Capacitance Min Typ Max 8pF 8pF Notes
AC ELECTRICAL CHARATERISTICS (1) TEST CONDITIONS
Parameter VCC Input pulse level Input rise and fall time Reference level Output loads Value 2.7-3.6V VIH=2.4V, VIL=0.4V 5ns VOH=VOL=1.5V 30pF Plus one TTL input load Notes
DQ
1 TTL Load
Cload including jig and scope
(2) READ CYCLE
Parameter tCR ta(A) ta(S) ta(OE) tdis(S) tdis(OE) ten(S) ten(OE) tv(A) Read cycle time (ns) Address access time (ns) Chip select access time (ns) Output e nable access time (ns) Output disable after /S (ns) Output disable after /OE (ns) Output enable after /S (ns) Output enable after /OE (ns) Data valid time after address CHD408LVS-55(-R) Min 55 5 5 10 Max 55 55 25 15 15 CHD408LVS-70(-R) Min Max 70 5 5 10 70 70 35 25 25 -
Deutron Electronics Corporation
8F, 68, SEC. 3, NAKING E. RD., TAIPEI 104, TAIWAN, R.O.C.
5
CHD408LVS-55,70 CHD408LVW-55,70
Rev 2.2 Jul'03
4M -BIT (512K-WORD BY 8-BIT) SuperT-SRAMTM LOW-POWER ASYNCHRONOUS SRAM
(3) WRITE CYCLE
Parameter tCW tw(W) tsu(A) tsu(A-WH) tsu(S) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) Write cycle time (ns) Write pulse width (ns) Address setup time (ns) Add setup to Write high (ns) Chip select setup time (ns) Data setup time (ns) Data hold time (ns) Write recovery time (ns) Output disable after /W (ns) Output disable after /OE (ns) Output enable after /W (ns) Output enable after /OE (ns) CHD408LVS-55(-R) Min 55 45 0 45 45 25 0 0 5 5 Max 25 25 CHD408LVS-70(-R) Min 70 55 0 55 55 25 0 0 5 5 Max 25 25 -
Deutron Electronics Corporation
8F, 68, SEC. 3, NAKING E. RD., TAIPEI 104, TAIWAN, R.O.C.
6
CHD408LVS-55,70 CHD408LVW-55,70
Rev 2.2 Jul'03
4M -BIT (512K-WORD BY 8-BIT) SuperT-SRAMTM LOW-POWER ASYNCHRONOUS SRAM
(4) TIMING DIAGRAMS
READ CYCLE
tCR A0-18 ta(A) /S ta(S) ta(OE) /OE /W = "H" level DQ1-8 ten(OE) ten tdis(OE) tdis(S) tv(A)
WRITE CYCLE (/W control mode)
tCW A0-18
/S
tsu(S)
/OE tsu(A) /W tdis(OE) DQ1-8 data in stable tsu(D) th(D) tsu(A-WH) tw(W) tdis(W) trec(W) ten(OE) ten(W)
Deutron Electronics Corporation
8F, 68, SEC. 3, NAKING E. RD., TAIPEI 104, TAIWAN, R.O.C.
7
CHD408LVS-55,70 CHD408LVW-55,70
Rev 2.2 Jul'03
4M -BIT (512K-WORD BY 8-BIT) SuperT-SRAMTM LOW-POWER ASYNCHRONOUS SRAM
WRITE CYCLE (/S control mode)
tCW A0-18 tsu(A) tsu(S) trec(W)
/S
/W
DQ1-8
data in stable tsu(D) th(D)
Deutron Electronics Corporation
8F, 68, SEC. 3, NAKING E. RD., TAIPEI 104, TAIWAN, R.O.C.
8
CHD408LVS-55,70 CHD408LVW-55,70
Rev 2.2 Jul'03
4M -BIT (512K-WORD BY 8-BIT) SuperT-SRAMTM LOW-POWER ASYNCHRONOUS SRAM
32-Pin 8x12mm sTSOP-I Package Dimensions
Unit: mm Symbol
Min 0.05 0.95 0.17 0.17 0.10 0.142 13.20 11.70 7.90 0.30 0.675 0 -
Nom 1.00 0.22 0.20 0.150 13.40 11.80 8.00 0.50 0.25 0.50 3 0.278
Max 1.25 1.05 0.27 0.23 0.21 0.158 13.60 11.90 8.10 0.70 5 0.075 -
A A1 A2 b b1 c c1 D D1 E e L1 L LE y s
Deutron Electronics Corporation
8F, 68, SEC. 3, NAKING E. RD., TAIPEI 104, TAIWAN, R.O.C.
9
CHD408LVS-55,70 CHD408LVW-55,70
Rev 2.2 Jul'03
4M -BIT (512K-WORD BY 8-BIT) SuperT-SRAMTM LOW-POWER ASYNCHRONOUS SRAM
32-Pin 8x20mm sTSOP-I Package Dimensions
Unit: mm Symbol
Min 0.05 0.95 0.17 0.17 0.10 0.10 19.80 18.20 7.80 0.50 0 -
Nom 1.00 0.22 0.20 20.00 18.40 8.00 0.50 0.60 0.80 REF 3 0.278
Max 1.20 0.15 1.05 0.27 0.23 0.16 0.16 20.20 18.60 8.20 0.70 5 0.075 -
A A1 A2 b b1 c c1 D D1 E e L LE y s
Deutron Electronics Corporation
8F, 68, SEC. 3, NAKING E. RD., TAIPEI 104, TAIWAN, R.O.C.
10
CHD408LVS-55,70 CHD408LVW-55,70
Rev 2.2 Jul'03
4M -BIT (512K-WORD BY 8-BIT) SuperT-SRAMTM LOW-POWER ASYNCHRONOUS SRAM
4M SuperT -SRAMTM CHD408LVx-55,70 Datashe et Revision History
Preliminary 0.1 Rev 1.0 2/21/02 WC 6/13/02 SC Preliminary initial version Added more detailed DC parameters and test conditions; fixed some DC parameter numbers. Added figure for output load Rev 1.1 Rev 2.0 Rev 2.1 Rev 2.2 1/2/03 SC Updated A17/A18 assignment to be consistent with industry convention. Added -55 grade Added 8x20mm TSOP-I package Renamed LVS-70W to LVW-70, to be consistent with naming convention.
3/20/03 JG 7/11/03 WC 7/22/03 WC
- The information contained herein is subject to change without notice.
Deutron Electronics Corporation
8F, 68, SEC. 3, NAKING E. RD., TAIPEI 104, TAIWAN, R.O.C.
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